The present invention relates generally to non-volatile memory devices and, more particularly, to a method and system of wordline voltage regulation in flash electrically erasable programmable read-only memory (EEPROM) devices.
Flash memories are popular memory storage devices because they store information in the absence of continuous power and are capable of being constructed in a very compact form. Flash memory is typically constructed by fabricating a plurality of floating-gate transistors in a silicon substrate. A floating-gate transistor is capable of storing electrical charge on a separate gate electrode, known as a floating gate that is separated by a thin dielectric layer from a control-gate electrode. Generally speaking, data is stored in a non-volatile memory device by the storage of an electrical charge in the floating gate.
In a flash EEPROM device, electrons are transferred to the floating-gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating-gate electrode and an underlying substrate. Typically, the electron transfer is carried out by channel hot electron (xe2x80x9cCHExe2x80x9d) injection or Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied to the control-gate electrode is coupled to the floating-gate electrode. In one type of device, the control-gate electrode is a polycrystalline silicon-gate electrode overlying the floating-gate electrode and separated therefrom by the thin dielectric layer. In another type of device, the floating-gate electrode is a doped region in the semiconductor substrate.
Flash memory is formed by rows and columns of flash transistors, with each transistor being referred to as a cell that includes a control gate, a drain and a source. A wordline decoder provides operational voltages to rows of transistors in each sector of the memory device and is typically connected with the control gate of each transistor in a sector. A bitline decoder provides operational voltages to columns of transistors and is typically connected to the drains of the transistors in each column. Generally, the sources of the transistors are coupled to a common sourceline and are controlled by a sourceline controller.
A cell is typically programmed by applying a predetermined voltage to the control gate, a second predetermined voltage to the drain, and grounding the source. This causes channel hot electrons to be injected from the drain depletion region into the floating gate. A cell can be erased several ways in a flash memory device. In one arrangement, a cell is erased by applying a predetermined voltage to the source, grounding the control gate and allowing the drain to float. This causes the electrons that were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source.
Cells are typically read during a read operation by applying a predetermined voltage to the control gate via a wordline, a second predetermined voltage to the bitline, to which the drain is connected, grounding the source, and then sensing the bitline current. If the cell is programmed and a threshold voltage is relatively high, the bitline current will be zero or relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low, the predetermined voltage on the control gate will enhance the channel and the bitline current will be relatively high.
Known problems occur during the read operation when a voltage applied to the wordline is not within a predetermined voltage range. If the voltage applied to the wordline decoder is too high, the cells on that wordline can be physically damaged or there can be a disturbance of the threshold voltage of the cells. In addition, applying a voltage that is too high can also cause data retention failure within the cells. High voltages on the wordline can also affect the endurance of the cells on a given wordline. If the wordline voltage is too low, insufficient bitline current may be developed to properly read a cell on the wordline.
Presently known methods of supplying voltage to the wordlines during the read operation use a supply voltage (Vcc) that is the power supply for the flash memory. As flash memory technology has advanced, and smaller technologies have been developed (0.25 micron process, for example), the acceptable magnitude of voltage allowed to be supplied to the wordlines during a read operation has been reduced. As such, the supply voltage (Vcc) necessary to operate the flash memory can no longer be directly applied to the wordlines without experiencing the problems associated with high wordline voltages as set forth above.
Another known problem with applying the wordline voltage necessary to perform the read operation exists because of the changes in the operating temperature of the flash memory. As the operating temperature of the flash memory changes, so do the wordline voltage often drifts during a read operation. Due to advances in the technology, the range of voltage required on the wordlines to perform the read operation has become narrower. Presently known methods of providing wordline voltages during read mode do not provide high-speed capabilities when the flash memory is accessed during the read operation, thereby slowing the access time of these memory devices.
To that end, due to the further miniaturization of microchips, a need exists for a method of wordline voltage regulation that provides a temperature-compensated predetermined output voltage that is less than the supply voltage (Vcc) during a read operation.
The present invention discloses a method and system of wordline voltage regulation in a flash memory that overcomes the problems caused by the further miniaturization of flash memories. The preferred flash memory includes a wordline driver circuit that regulates a supply voltage (Vcc) to provide a predetermined temperature-compensated wordline voltage that can be applied to a plurality of wordlines during a read operation. The wordline driver circuit is capable of reducing the magnitude of voltage available on the supply voltage (Vcc) to a level that is acceptable to perform read operations in the flash memory.
The present invention discloses a method of supplying a predetermined read voltage when a flash memory device is in read mode. In the preferred embodiment of the invention, a plurality of control signals are generated with an activation circuit, in response to control signals received by a state machine. The control signals are directed to a wordline driver circuit, which generates a predetermined read voltage using a supply voltage connection in response to the control signals. In the preferred embodiment, the wordline driver circuit reduces the voltage level from the magnitude of voltage present on the supply voltage connection with the wordline driver circuit. After being reduced, the predetermined read voltage is supplied to at least one wordline in the flash memory device during the read operation.
In the preferred embodiment of the invention, the wordline driver circuit generates the predetermined read voltage using a chain of resistors and a current mirror. The wordline driver circuit adjusts for variations in the voltage level on the supply voltage connection to maintain the predetermined read voltage at acceptable levels. In the present preferred embodiment, the predetermined read voltage is maintained between approximately 3.7-4.5 V when the voltage level on the supply voltage connection is operating between approximately 4.5-5.5 V. The wordline driver circuit regulates the voltage on the supply voltage connection to the predetermined read voltage within ten nanoseconds once the activation circuit is activated by the state machine.
Another preferred embodiment of the present invention discloses a method of regulating a supply voltage in a memory device that is operating in read mode. In this embodiment, the supply voltage is supplied to a wordline driver circuit within the flash memory device. The wordline driver circuit is activated with an activation circuit when the memory device is in read mode. Once activated, the supply voltage is regulated to a predetermined read voltage with the wordline driver circuit. After the predetermined read voltage is regulated to a predetermined level, the predetermined read voltage is supplied to at least one wordline in the flash memory device.
Another preferred embodiment of the present invention discloses a wordline voltage regulation system for use during read mode in a flash memory device. The voltage regulation system includes an activation circuit electrically connected with a state machine. The state machine controls the activation circuit with a plurality of control signals that are connected to the activation circuit using a plurality of control lines. A wordline driver circuit is electrically connected to the activation circuit. The wordline driver circuit regulates the voltage on the supply voltage connection to a predetermined read voltage in response to a signal from the activation circuit. At least one wordline is electrically connected with the wordline driver circuit, which provides the predetermined read voltage to at least one wordline during read mode.
The preferred embodiments of the present invention disclose methods and systems that quickly and accurately provide a predetermined read voltage to wordlines in a flash memory device during read mode. The present invention overcomes the problems created with reduced transistor sizes, such as 0.25 um transistor sizes, and the exposure of these transistors that make up the memory cells in wordlines to voltage levels that may disturb the data stored in these memory cells. The present invention discloses a wordline driver circuit that can provide a reduced predetermined read voltage to wordlines in a flash memory device within 10 nanoseconds of activation that will not disturb the data stored on the memory cells in the wordlines. As such, the present invention solves the problems created by applying voltage levels that are to high on the wordlines during read mode in a flash memory device.
These and other features and advantages of the invention will become apparent upon consideration of the following detailed description of the presently preferred embodiments of the invention, viewed in conjunction with the appended drawings.